Bit error rate measurement apparatus
US5623497A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1995 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Feb 9, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/244
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bit error measurement apparatus is capable of easily specifying pattern conditions which cause bit errors in an incoming signal pattern without measuring all of a test pattern by measuring a bit error rate at a selected position or region of a test pattern. The bit error measurement apparatus includes a test pattern generator which generates the test pattern for verifying the incoming signal to be tested, a verifier which receives the incoming signal and the test pattern and generates a bit error detection signal when the incoming signal and the test pattern disagree, a pattern position detector which detects a measurement region of the test pattern when receiving a synchronizing signal from the test pattern generator and generates a count enable signal corresponding to the detected measurement region, and an error counter which counts the bit error detection signal from the verifier based on the count enable signal from the pattern position detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.