System and method for improving multilevel cache performance in a multiprocessing system
US5623632A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 1995 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | May 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system having a plurality of bus devices coupled to a storage device via a bus, wherein the plurality of bus devices have a snoop capability, and wherein the plurality of bus devices have first and second caches, and wherein the plurality of bus devices utilize a modified MESI data coherency protocol, the system provides for reading of a data portion from the storage device into one of the plurality of bus devices, wherein the first cache associated with the one of the plurality of bus devices associates a special exclusive state with the data portion, and wherein the second cache associated with the one of the plurality of bus devices associates an exclusive state with the data portion, initiating, by the one of the plurality of bus devices, a write-back operation with respect to the data portion, determining if there are any pending snoops in the second cache, and changing the special exclusive state to a modified state if there are no pending snoops in the second cache. If there is a pending snoop in the second cache, a comparing of addresses of the pending snoop and the data portion is performed. The special exclusive state is changed to a modified state if …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.