Data processing system and method for providing memory access protection using transparent translation registers and default attribute bits
US5623636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1993 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Nov 9, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system (10 or 28) and method uses a memory management unit (MMU 14). The processor has two privileged modes of operations, such as a user mode and a supervisor mode of operation. The MMU 14 has a first mode of operation wherein logical address translation is performed via cache accesses and tablewalks, and a second mode of operation. The second mode of operation involves providing translation attribute bits from one of either a first transparent translation register (TTR 16), a second transparent translation register (TTR 18), or a default location (22). The TTRs (16 and 18) can each map different address spaces and different addressed memory sizes and the default location (22) covers all memory that is not mapped by one of the TTRs (16 or 18). The default location (22) is programmable, provides write protection, and provides attribute bits independent from the privilege mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.