Interface circuit having zero latency buffer memory and cache memory information transfer
US5623700A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1994 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Apr 6, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A caching disk controller is provided which includes a bus bridge that forms an interface between a memory of the disk controller and a host computer. The caching disk controller further includes a SCSI processor for controlling the transfer of data from a SCSI disk drive to the memory via a local bus. A zero latency DMA controller embodied within the bus bridge snoops the local bus as data is being transferred from the SCSI disk drive to the memory, and thereby allows the data to be sequentially latched within a data FIFO of the bus bridge concurrently with its transfer into the memory. As a result, the requested data may be advantageously provided from the bus bridge to the host computer with reduced delay, while the data continues to be stored within the memory to accommodate high hit rates during subsequent transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.