Separate I.sub.DDQ -testing of signal path and bias path in an IC
US5625300A · kind A · utility
14Cited by
5References
10Claims
0Family size
Inventor
Key dates
| Filing date | Dec 14, 1994 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Dec 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3008
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An IC is tested through I.sub.DDQ -measurements. The IC's substrate includes a region of a conductivity type with a supply node for supply of the circuit and with a biasing node for connection to a biasing voltage to bias the region. I.sub.DDQ -testing of the circuit is conducted while the supply node and the biasing node are galvanically disconnected to separate the contribution to the quiescent current from the circuit functionality features from the contribution to the quiescent current from the biasing features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.