Method and apparatus for compacting integrated circuits with standard cell architectures
US5625568A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1994 |
| Grant date | Apr 29, 1997 |
| Priority date | — |
| Expiry date | Sep 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-aided design system for compacting an integrated circuit layout with standard cell components is described. A data receiving device is used to process an integrated circuit layout that includes standard cell components. The integrated circuit layout is characterized by a circuit layout database with a cell table defining a set of cells that represent all spaces in the integrated circuit layout. The cell table includes connector cell data to indicate whether a cell forms a portion of a connected group of cells. The system includes an adjustment mechanism to align internal connectors of a standard cell with a routing grid associated with the integrated circuit layout. The system also includes a movement mechanism to position right-edge external connectors of a standard cell at a uniform routing grid coordinate position. The system uses the connector cell data to identify a power bus and a ground bus of each standard cell. Thereafter, a minimum edge to edge distance is assigned to each power bus and each ground bus. The connector cell data is also used to identify second metal plane routing paths. The system repositions selected second metal plane routing paths to increase …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.