Trench method for three dimensional chip connecting during IC fabrication
US5627106A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 6, 1994 |
| Grant date | May 6, 1997 |
| Priority date | — |
| Expiry date | May 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of connecting three-dimensional integrated circuit chips using trench technology is described. Semiconductor device structures are provided in and on the top side of a semiconductor substrate of a first and a second three-dimensional integrated circuit chip. Deep trenches are etched into the first semiconductor substrate. A conductive material is deposited into the trenches. An insulating material is deposited over the surface of the substrate, polished and planarized. The bottom side of the first semiconductor substrate is ground, polished, and selectively etched so that the deep trenches form protrusions from the bottom surface. A passivation layer and a polyimide layer are deposited on the bottom surface of the first semiconductor substrate and etched away around the protrusions. A passivation layer and a polyimide layer are deposited over the top surface of the second semiconductor substrate. Connection windows are etched through the two layers to the top conducting surface of the second semiconductor substrate. The first and second integrated circuits are aligned so that the protrusions on the bottom surface of the first integrated circuit chip fit into the connec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.