Semiconductor device with columns

US5627390A · kind A · utility

Assignee

• Mitsubishi Electric Corporation · JP

Inventors

• Shigenobu Maeda · Kasai, JP
• Yasuo Inoue · Odawara, JP
• Hirotada Kuriyama · Kasai, JP
• Shigeto Maegawa · Tokyo, JP
• Kyozo Kanamoto · Tokyo, JP
• Toshiaki Iwamatsu · Tokyo, JP

Key dates

• Filing date: May 16, 1996
• Grant date: May 6, 1997
• Expiry date: May 16, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00

Abstract

A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.