Speculative and committed resource files in an out-of-order processor
US5627985A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1994 |
| Grant date | May 6, 1997 |
| Priority date | — |
| Expiry date | Jan 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.