Pipelined processor with register renaming hardware to accommodate multiple size registers
US5630149A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 20, 1995 |
| Grant date | May 13, 1997 |
| Priority date | — |
| Expiry date | Nov 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, wherein one or more of the instructions reference a defined set of logical registers having multiple addressable sizes as sources and destinations of operands for the instruction. A plurality of physical registers are provided in excess of the number of defined set of logical registers. Physical registers are selectively allocated to one of said defined set of logical registers responsive to an instruction for writing to said one of said logical registers and the size associated with the logical register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.