Carry Selecting system type adder
US5631860A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | May 20, 1997 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder including a first exclusive OR device, a second exclusive OR device for receiving an output of the first exclusive OR device and a generating signal G(i-1), exclusive ORing the output result of the first exclusive OR device and the generating signal G(i-1), and outputting the calculated result as a sum Si0, and a third exclusive OR device for receiving an output of the second exclusive OR device and a propagating signal P(i-1), exclusive ORing the output result of the second exclusive OR device and the propagating signal P(i-1), and outputting the calculated result as a sum Si1, whereby the amount of hardware and power consumption of the adder used in a carry selecting system is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.