Edge triggered set-reset flip-flop (SRFF)
US5633607A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1995 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Apr 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/58
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timer comprised of first and second gated SR (set-reset) latches each including two pair (S1, S2 and R1, R2) of inputs and a pair of outputs (Q, QN), the Q output of the first latch being connected to the R2 input of the second latch, and the QN output of the first latch being connected to the S2 input of the second latch, the Q output of the second latch being connected to the S2 input of the first latch, and the QN output of the second latch being connected to the R2 input of the first latch, apparatus for applying a delayed representation of a first pulse signal to the S1 input of the first latch and apparatus for applying a delayed representation of a second pulse signal to the R1 input of the first latch, apparatus for applying an inverted representation of the pulse signal to the S1 input of the second latch and apparatus for applying an inverted representation of the second pulse signal to the R1 input of the second latch, whereby timed output signals representing a differential between leading edges of the first and second pulse signals are provided at the outputs Q, QN of the second latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.