Fault simulation of testing for board circuit failures
US5633812A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1992 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Sep 29, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of accurately simulating how design defects and faults are detected in the board design and manufacturing test environments is provided which uses statements in the simulation control language of a fault simulator. The simulation of the operation of electronic boards (which may not yet have been built) in their expected test environments is possible. The set of statements used in the simulation language allows the proposed functional self-test code, also called diagnostic code or power-on self-test code, which is to be executed by a (micro-)processor, to be tested for its effectiveness. The simulation must synchronize the simulated execution of the processor code to be evaluated with the fault detection by the code being evaluated, simulate the use of any attached tester, such as a logic analyzer, and provide data that can be used for programming devices in the test environment. The PROBE statements in the simulation language determine when the simulator starts and ends a measurement window during which faults can be detected by the simulator. These statements can be used to simulate the amount of time a net must remain stable for test equipment to capture its value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.