Inexact leading-one/leading-zero prediction integrated with a floating-point adder
US5633819A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1995 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Oct 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/503
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The sum from a floating point adder is normalized by an initial shift based on a prediction for the position of the leading one or zero in the sum. This leading-one/zero prediction is based not on the operands input to the adder, nor the result from the adder, but on the intermediate generate and propagate signals within the adder. The adder has a first stage that reduces each bit-position to a generate and a propagate signal. The adder's second stage propagates the carries in the adder using these generate and propagate signals to generate the sum. Thus the adder's first-stage logic is also used for the leading one/zero prediction, reducing cost and complexity. An ECL half-adder cell is preferably used for the adder's first stage. A zero output is added to the ECL half-adder cell at minimal cost. The shift for the leading one/zero prediction is accomplished in two stages, with a selective complement of negative sums between the two-stage shift. This allows more time for a more exact prediction after the first coarse shift. The final exact detection of the leading one is pipelined to detect the sum after the complementor but before the second stage of the shifter. This allows the f…
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