Error detection and correction circuit
US5633882A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1996 |
| Grant date | May 27, 1997 |
| Priority date | — |
| Expiry date | Mar 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/15
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention addresses the need in the art by providing a novel approach to the correction of errors in check bits in an encoded data word. The invention consists of a check bit output latch 16 which stores check bits generated by a check bit generator 14 and outputs the newly generated check bits to memory 12 when a single error occurs in the word located in the check bits. The data is corrected so the newly generated check bits are correct and can be latched out to memory 12 at the same time the data is latched out. The invention includes a syndrome generator 18, an error corrector 34, and an error detector 36. The present invention provides a powerful performance boost to error detection and correction circuits by correcting check bits in memory with newly generated check bits when no errors in the data word are detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.