Global planarization using a polyimide block
US5635428A · kind A · utility
7Cited by
9References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1994 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Oct 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes conductor regions 24 and 26 on a layer of the semiconductor device; a first insulator layer 28 over and between the conductor regions 24 and 26; polyimide regions 30, 32, and 34 over the first insulator layer 28 in gaps between the conductor regions 24 and 26; and a second insulator layer 38 over the first insulator layer 28 and over the polyimide regions 30, 32, and 34. A surface of the second insulator layer 38 is substantially planar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.