SRAM cell with no PN junction between driver and load transistors and method of manufacturing the same
US5635731A · kind A · utility
20Cited by
1References
10Claims
0Family size
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Key dates
| Filing date | Aug 7, 1995 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Aug 7, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
SRAM memory cells is provided with high resistance to soft error and no parasitic capacitance due to PN junction. SRAM memory cells comprises the load resister is a thin film transistor having a same conductive type as that of the driver transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.