Multi-layer gate structure
US5635765A · kind A · utility
17Cited by
4References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1996 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Feb 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBiotechnology
- WIPO sectorChemistry
Abstract
A method of forming a multi-layer silicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.