Method for programming complex PLD having more than one function block type
US5636368A · kind A · utility
97Cited by
20References
22Claims
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Key dates
| Filing date | Dec 23, 1994 |
| Grant date | Jun 3, 1997 |
| Priority date | — |
| Expiry date | Dec 23, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing both "fast" function blocks (FFBs) and "high density" function blocks (HDFBs) are programmed such that the FFBs are programmed prior to the HDFBs. This method maximizes the overall speed of an implemented logic function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.