Method of manufacturing semiconductor device having multilevel interconnection structure
US5637534A · kind A · utility
11Cited by
16References
64Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1993 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Dec 27, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a multilayered structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and a via hole. The semiconductor device is manufactured by a method that includes plasma etching at least one surface of the insulating interlayer the in an atmosphere having as a major component either a carbonless, chlorine-based gas or a carbonless, chlorine-based gas and an inactive gas in order to remove contaminates that would otherwise promote reactivity with aluminum CVD on the surface of the insulating interlayer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.