Patent · US Expired

Three-dimensional monolithic electronic module having stacked planar arrays of integrated circuit chips

US5637912A · kind A · utility

41Cited by
11References
12Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 31, 1996
Grant dateJun 10, 1997
Priority date
Expiry dateMay 31, 2016

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.