Nonvolatile semiconductor memory using tunnel effect having a control circuit for simultaneously writing and reading data out of a plurality of memory cells
US5638323A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1995 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Apr 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3486
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each of the memory cells is provided at each intersection of the bit lines and the word lines. The nonvolatile semiconductor memory includes a plurality of latch units provided for each corresponding bit line, and a control circuit. The control circuit is used to supply a control voltage and a control signal to the latch units, to operate the latch units as units for simultaneously biasing voltages applied to first electrodes of specified memory cells through the bit lines during a write operation, to simultaneously write data into the specified memory cells, and during a read operation, as units for simultaneously reading data out of the memory cells. This memory has an inexpensive simple structure for carrying out a simple programming operation at high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.