Flash-EEPROM memory array and method for biasing the same
US5638327A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1995 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Mar 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash-EEPROM memory array presenting a NOR architecture wherein the memory cells, organized in rows and columns and having drain regions connected to respective bit lines, source regions connected to a common source line, and control gate regions connected to respective word lines, present an asymmetrical structure wherein one of the source and drain regions presents a highly resistive portion to permit programming and erasing of the cells at different regions. The array includes bias transistors arranged in a row and each connected between a respective bit line and the common source line, for maintaining at the same potential the drain and source regions of the cells connected to the nonaddressed bit lines during programming, and so preventing spurious writing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.