Integrated circuit I/O using a high performance bus interface
US5638334A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1995 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | May 24, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.