Built-in self test function for a processor including intermediate test results
US5638382A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1994 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Jun 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor with a built in self test function that provides intermediate self test results is disclosed including at least one logic array and a test circuit for each logic array coupled to generate a logic array signature during a built in self test of the processor. The processor further comprises a set of internal registers including a performance register that stores the logic array signature and a register that stores a pass/fail indication for the built in self test of the processor. The internal registers also store a pass/fail indication for a cache memory built in self test and a pass/fail indication for a constant read only memory built in self test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.