Method of fabricating a wafer probe card for testing an integrated circuit die
US5639385A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed. The present invention further provides a wafer probe card which includes a multi-layer, relatively flexible tape-like substrate having a first conductive layer patterned to have a number of probe leads thereon. The first conductive layer of probe lea…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.