Self-enabling latch
US5640115A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1995 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Dec 1, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-enabling latch includes a pair of pass transistors, a pair of cross-coupled inverters, an EXCLUSIVE-NOR logic gate and a differential amplifier. The pass transistors receive a differential input data signal which is selectively latched by the cross-coupled inverters. The EXCLUSIVE-NOR logic gate also receives the input data signal and compares it with the latched data signal to provide a control signal for the amplifier. The control signal is active when the present input data is different from the previously latched data. The amplifier, enabled by the active control signal, amplifies a differential clock signal to provide an enabling signal for the pass transistors which thereby present the new input data to the cross-coupled inverters for latching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.