Programmable built-in self-test function for an integrated circuit
US5640509A · kind A · utility
56Cited by
9References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 3, 1995 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Oct 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for providing programmable self-testing in a memory. Registers in the memory are programmed with a sequence of instructions for performing the self-test of the memory. The sequence of instructions is run to perform the self-test of the memory, and the results are checked. The memory includes a clock multiplier which allows the registers to be programmed at a first clock rate, then the memory is tested at a second clock rate which is faster than the first clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.