Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme
US5640519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1995 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Sep 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arbitration circuit which controls arbitration for a resource by a first plurality of agents including a latency sensitive agent. The arbitration circuit comprises a mapping circuit and an arbiter. The mapping circuit is coupled to the first plurality of agents in order to receive a resource request signal from the latency sensitive agent and thereafter produce a plurality of request signals identical to the resource request signal. These request signals are input into at least a first and second I/O ports of the arbiter. The arbiter, which is coupled to the mapping circuit, including a second plurality of I/O ports and a second plurality of control ports each corresponding to one of the I/O ports. The arbiter is configured to arbitrate request signals input into the second plurality of I/O ports including the plurality of request signals, to monitor which I/O port was last activated, and to deactivate a control port associated with the I/O port thereby producing a control signal. This control signal signals the mapping circuit to disable at least one of the plurality of request signals upon detecting that the control signal is associated with the first I/O port or the second I/…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.