James M. Dodd
40Patents
18h-index
24Co-inventors
77Inventor score
Filing activity: Sep 15, 1995 → Sep 15, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6742098B1 | Dual-port buffer-to-memory interface | Physics | 347 | Expired |
| US6795899B2 | Memory system with burst length shorter than prefetch length | Physics | 201 | Expired |
| US6493250B2 | Multi-tier point-to-point buffered memory interface | Physics | 158 | Expired |
| US6618791B1 | System and method for controlling power states of a memory device via detection of a chip select signal | Emerging Cross-Sectional Technologies | 155 | Expired |
| US7024518B2 | Dual-port buffer-to-memory interface | Physics | 129 | Expired |
| US6639820B1 | Memory buffer arrangement | Physics | 98 | Expired |
| US6981089B2 | Memory bus termination with memory unit having termination control | Physics | 95 | Expired |
| US6862653B1 | System and method for controlling data flow direction in a memory system | Physics | 77 | Expired |
| US6449213B1 | Memory interface having source-synchronous command/address signaling | Physics | 70 | Expired |
| US6530006B1 | System and method for providing reliable transmission in a buffered memory system | Physics | 65 | Expired |
| US6507530B1 | Weighted throttling mechanism with rank based throttling for a memory system | Physics | 44 | Expired |
| US6553449B1 | System and method for providing concurrent row and column commands | Emerging Cross-Sectional Technologies | 39 | Expired |
| US6952745B1 | Device and method for maximizing performance on a memory interface with a variable number of channels | Physics | 31 | Expired |
| US6772352B1 | Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curve | Physics | 30 | Expired |
| US6505282B1 | Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics | Physics | 24 | Expired |
| US5603010A | Performing speculative system memory reads prior to decoding device code | Physics | 22 | Expired |
| US6781911B2 | Early power-down digital memory device and method | Physics | 22 | Expired |
| US6725349B2 | Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory | Physics | 18 | Expired |
| US6212589A | System resource arbitration mechanism for a host bridge | Physics | 18 | Expired |
| US5640519A | Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme | Physics | 17 | Expired |
| US7120765B2 | Memory transaction ordering | Physics | 17 | Expired |
| US5894567A | Mechanism for enabling multi-bit counter values to reliably cross between clocking domains | Physics | 16 | Expired |
| US6766385B2 | Device and method for maximizing performance on a memory interface with a variable number of channels | Physics | 15 | Expired |
| US6801459B2 | Obtaining data mask mapping information | Physics | 10 | Expired |
| US6148380A | Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus | Physics | 9 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.