Power management message bus for integrated processor
US5640573A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1994 |
| Grant date | Jun 17, 1997 |
| Priority date | — |
| Expiry date | Feb 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor depending upon the system requirements. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an outside power management unit. The power management message bus is channeled from the integrated processor at a set of package pins that are isolated from the standard external peripheral bus of the integrated processor. By providing encoded information regarding the internal events of the integrated processor, monitoring of such events by an external power management unit is possible while the number of external pins on the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.