Method of forming diffusion layer and method of manufacturing nonvolatile semiconductor memory device
US5641696A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1995 |
| Grant date | Jun 24, 1997 |
| Priority date | — |
| Expiry date | Aug 25, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
The first impurity species having a low diffusion rate is heavily doped in a predetermined region of a semiconductor substrate in contact with portions corresponding to the edges of a floating gate, and the second impurity species having a low diffusion rate is lightly doped in the predetermined region from a position separated from the portions corresponding to the edges of the floating gate by a predetermined distance. Annealing is performed such that the second impurity species is diffused below the floating gate more inward than the first impurity species, and part of a diffusion region formed by the first impurity species serves as a tunnel region which overlaps the floating gate. With this structure, a short channel effect can be prevented, and an inter-band current can be suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.