Method of manufacturing a semiconductor device having a dummy cell
US5641699A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1995 |
| Grant date | Jun 24, 1997 |
| Priority date | — |
| Expiry date | Jul 14, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
Abstract
In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region. At last one of dummy cells is made to be a P-N lacking dummy cell having a semiconductor element in construction including at least a gate and excluding at least one of P-N junction parts from the same construction as the field effect semiconductor element in the active cells. All dummy cells may be the P-N lacking dummy cells. Thereby, insulation defects through the P-N lacking dummy cell due to distu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.