Method for producing a semiconductor layer structure having a planarized surface and the use thereof in the manufacture of bipolar transistors and DRAMS

US5643836A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Thomas Meister · Taufkirchen, DE
• Reinhard Stengl · Stadtbergen, DE

Key dates

• Filing date: Jul 22, 1994
• Grant date: Jul 1, 1997
• Expiry date: Jul 22, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31055
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An insulating layer is applied onto the surface of a semiconductor layer structure having elevations up to a maximum step height. The thickness of the insulating layer is greater than the maximum step height. The insulating layer is structured to have irregularities with an essentially identical lateral expanse in the region of the edges of the elevations. The irregularities are planarized by chemical mechanical polishing and/or by deposition, flowing and etch-back of a planarization layer.