Method for etching nitride features in integrated circuit construction
US5644153A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Oct 31, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for etching nitride layers in three steps is disclosed. The process comprises selecting a process chemistry of CF.sub.4 to CHF.sub.3 to set a predetermined critical dimension bias; conducting a primary etch of the process chemistry which will have a high etch rate; and conducting a secondary etch of ion bombardment having a lower etch rate and high selectivity to pad oxide. In selecting the process chemistry, selecting greater amounts of CHF.sub.3 will result in higher polymer concentration on the etched sidewall. Varying the pressure and power can also be used to vary the polymer concentration. This in turn is used to select the desired critical dimension bias. The secondary etch uses a mixture of NF.sub.3 and HBr and is performed at a high pressure and a low power to promote high nitride to oxide selectivity. The secondary etch removes the majority of polymer from the nitride sidewalls and cleans the polymer from the chamber walls, resulting in an anisotropic etch and a high number of wafers produced before cleaning is necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.