Mold and method for manufacturing a package for a semiconductor chip and the package manufactured thereby
US5644169A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 1996 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Apr 3, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mold and a method for manufacturing a semiconductor package and the semiconductor package manufactured thereby. The semiconductor package includes a chip attached to a paddle of a lead frame. And with electrically connecting the chip and inner leads of lead frame with a metal wire, a semi-finished product having electric connections is molded by using molding dies having an extrusion in a cavity for providing an opening on an upper portion of a light receiving region of the chip, and a transparent lid is provided on the upper portion of the opening of the semiconductor package. With the invention being able to provide an excellent resin semiconductor package and improved manufacturing processes, thereby reducing the manufacturing cost, enhancing a productivity and making a manufacturing process simpler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.