Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
US5644251A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Sep 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.