Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses
US5644496A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1993 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Jun 18, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP's) are distributed symmetrically among the N.multidot.M crosspoints such that a same first number of interconnect switches (PIP's) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP's) are further distributed among the N.multidot.M crosspoints such that a same second number of interconnect switches (PIP's) are found along each of the M output lines thereby providing equal loading on each output line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.