Flash memory system, and methods of constructing and utilizing same
US5644533A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Apr 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An N-channel SNOS or SONOS type memory array (100) has programmable states with a negative, depletion mode threshold lower in magnitude than the supply voltage V.sub.CC when erased and a positive threshold when programmed. During reading, the supply voltage V.sub.CC is applied to the drain (16), while a positive voltage V.sub.R less than V.sub.CC -V.sub.ds,sat is applied to the source (14), where V.sub.ds,sat is the saturation voltage of the device. A reference voltage may also be applied to the substrate (11) during a read operation. Selected devices have V.sub.R applied to the gate (12), while inhibited devices have ground or the substrate potential V.sub.SS applied to the gate (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.