Multiple port high speed register file with interleaved write ports for use with very long instruction word (vlin) and n-way superscaler processors
US5644780A · kind A · utility
18Cited by
14References
13Claims
0Family size
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Key dates
| Filing date | Jun 2, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Jun 2, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed register file is provided for use with Very Long Word Instruction (VLIW) and N-way superscaler processors. The high speed register file includes a selected number of copies of a general purpose register (GPR) building block. The GPR building block includes at least two interleaved sub-banks of registers. Each of the sub-banks includes a number N of write ports and a number M of read ports. The sub-banks are interleaved by write ports and have non-interleaved read ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.