David Arnold Luick
107Patents
19h-index
44Co-inventors
86Inventor score
Filing activity: Oct 23, 1978 → Feb 27, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5812817A | Compression architecture for system memory application | Physics | 106 | Expired |
| US6223208A | Moving data in and out of processor units using idle register/storage functional units | Physics | 101 | Expired |
| US5625835A | Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor | Physics | 89 | Expired |
| US6314493A | Branch history cache | Physics | 87 | Expired |
| US6230260A | Circuit arrangement and method of speculative instruction execution utilizing instruction history caching | Physics | 54 | Expired |
| US7086058B2 | Method and apparatus to eliminate processor core hot spots | Emerging Cross-Sectional Technologies | 47 | Expired |
| US5924117A | Multi-ported and interleaved cache memory supporting multiple simultaneous accesses thereto | Physics | 41 | Expired |
| US7487340B2 | Local and global branch prediction information storage | Physics | 41 | Active |
| US7174469B2 | Processor power and energy management | Emerging Cross-Sectional Technologies | 41 | Expired |
| US6088769A | Multiprocessor cache coherence directed by combined local and global tables | Physics | 36 | Expired |
| US5805850A | Very long instruction word (VLIW) computer having efficient instruction code format | Physics | 31 | Expired |
| US7089370B2 | Apparatus and method for pre-fetching page data using segment table data | Physics | 30 | Expired |
| US7117389B2 | Multiple processor core device having shareable functional units for self-repairing capability | Physics | 30 | Expired |
| US6112299A | Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching | Physics | 29 | Expired |
| US5872990A | Reordering of memory reference operations and conflict resolution via rollback in a multiprocessing environment | Physics | 24 | Expired |
| US5890009A | VLIW architecture and method for expanding a parcel | Physics | 22 | Expired |
| US7124318B2 | Multiple parallel pipeline processor having self-repairing capability | Physics | 22 | Expired |
| US7219185B2 | Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache | Physics | 21 | Expired |
| US7237094B2 | Instruction group formation and mechanism for SMT dispatch | Physics | 20 | Expired |
| US5644780A | Multiple port high speed register file with interleaved write ports for use with very long instruction word (vlin) and n-way superscaler processors | Physics | 18 | Expired |
| US7487330B2 | Method and apparatus for transferring control in a computer system with dynamic compilation capability | Physics | 18 | Expired |
| US7188227B2 | Adaptive memory compression | Physics | 16 | Expired |
| US6473835B2 | Partition of on-chip memory buffer for cache | Physics | 16 | Expired |
| US6912649B2 | Scheme to encode predicted values into an instruction stream/cache without additional bits/area | Physics | 15 | Expired |
| US7099999B2 | Apparatus and method for pre-fetching data to cached memory using persistent historical page table data | Physics | 15 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.