Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages
US5646548A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 1996 |
| Grant date | Jul 8, 1997 |
| Priority date | — |
| Expiry date | Feb 14, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit receives and transmits signals at more than one set of VH/VL voltage levels. The integrated circuit includes a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines each at power supply voltage levels V1, V2, V3 . . . Vm. The integrated circuit also includes input circuitry and output circuitry each of which have buffers and translators. The availability of the power lines each at power supply voltage levels V1, V2, V3 . . . Vm and translators allows for the present circuit to transmit and receive various sets of input signals and output signals, all within the same integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.