Pipeline structure using positive edge and negative edge flip-flops to decrease the size of a logic block
US5646555A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 25, 1995 |
| Grant date | Jul 8, 1997 |
| Priority date | — |
| Expiry date | Oct 25, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To obtain a semiconductor integrated circuit reduced in hardware size, by avoiding duplication of a common constitution. A logic block (100) comprises logic means (A), logic means (B), and logic means (C), and the output of a pipeline register (11) is connected to the logic means (A) through a signal line (a), and the logic means (A) and logic means (B) are connected through a signal line (b). The logic means (A) is also connected to the logic means (C) through a signal line (c), and the logic means (C) is connected to the input of a pipeline register (21) through a signal line (d). When performing the same logic action in the first half period and second half period of a clock signal, it is not necessary to install two identical logic means, so that the size of the hardware may be reduced as compared with the constitution of installing two identical logic means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.