Delta-sigma ADC with multi-stage decimation filter and gain compensation filter
US5646621A · kind A · utility
121Cited by
34References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1994 |
| Grant date | Jul 8, 1997 |
| Priority date | — |
| Expiry date | Nov 2, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital conversion circuit is described which includes a front end sigma-delta modulator circuit, a multi-stage digital decimation filter circuit, and a digital compensation filter circuit. An overrange detect circuit is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.