Multiplication/multiplication-accumulation method and computing device
US5646874A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1994 |
| Grant date | Jul 8, 1997 |
| Priority date | — |
| Expiry date | Dec 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a computing device for the multiplication/multiplication-accumulation of signed numbers, respectively of N bits and N-1 bits, generated a subword of N bits selectable from the result of 2N-1 bits using a multiplier/multiplier-accumulator incorporating a register file connected to an arithmetic and logic unit by a first bus and a second bus via a barrel shifter. The output of the arithmetic and logic unit is connected to the register by a third bus. A Booth Finite State Machine (FSM) is connected to the first bus. A partial product is realigned with respect to an operand A and an Arithmetical Shift Right (ASR) according to the following relation: product=ASR (product, align).+-.operand.sub.-- A. The cycles of a second type ar repeated until the partial product has been shifted by a number of bits corresponding to the desired subword position. Cycles of a first type are performed, such as to obtain, with respect to a Logical Shift Left (LSL), the relation: product=product.+-.LSL (operand.sub.-- A, align). The alignment quantity and the arithmetic operation are determined by the control FSM according to the Booth decoding of an operand B.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.