Static random access memory device with low power dissipation
US5646902A · kind A · utility
24Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 3, 1996 |
| Grant date | Jul 8, 1997 |
| Priority date | — |
| Expiry date | Jul 3, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory device having a power-down timer for generating a power-down signal in response to a plurality of address transition detecting signals and data input detecting signals, a chip selection detecting signal and a write mode detecting signal, is disclosed. The device includes a power-up detector for generating a power-up signal to make the power-down detecting signal be conducted, the power-up detecting signal responding to a rising of a power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.