Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
US5648661A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1994 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Sep 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/4813
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Unsingulated dies on a wafer may be individually electronically selected using various "electronic mechanisms" on the wafer. Conductive lines extend on the wafer from the electronic mechanism to the individual dies. The conductive lines may be provided in sets of two or more, such as for providing discrete power and ground connections from the external equipment to the individual dies. Redundant conductive lines may be provided to ensure against "open" faults. Diode and/or fuses may also be provided in conjunction with the conductive lines to ensure against leakages and shorts. Redundant electronic selection mechanisms may also be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.