Field programmable pipeline array
US5648732A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 4, 1995 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Oct 4, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) for implementing pipelined designs is described. A pipeline array of registers and function generators, comprises registers and function generators arranged along a line in a first direction, the first direction being a direction of propagation of data signals, and registers and function generators arranged along a line in a second direction, the second direction being a direction of propagation of carry signals and control signals. Each of said function generators is operatively connected by routing resources to at least two of the registers within the pipeline array. A synchronization ring of the PLD comprises shift registers, each of the shift registers being programmable such that its bit length can be adjusted from one bit to a predefined maximum number of bits. The synchronization ring surrounds and is operatively connected by routing resources to the pipeline array. An Input/Output (I/O) ring of the PLD comprises programmable logic resources for processing signals entering and exiting the PLD. The I/O ring surrounds and is operatively connected by routing resources to the synchronization ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.