Sigma-delta modulator having reduced delay from input to output
US5648779A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 1994 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Dec 9, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3022
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described herein is a fourth-order sigma-delta modulator which utilizes two second-order sigma-delta modulators connected together. Each second-order sigma-delta modulator is characterized as including integrators having a 1/2 sample period delay from input to output. A second-order sigma-delta modulator, including such integrators, exhibits a single sample period delay from input to output. A fourth-order sigma-delta modulator, which includes two such second-order sigma-delta modulators, exhibits a delay of two sample periods from input to output. The present sigma-delta modulator can be fabricated using switched capacitor circuitry to form an A/D convertor, and in another embodiment can be used as a digital noise shaper for a D/C convertor circuit. The 1/2 unit delay is implemented without requiring two D-flip flops in series, which results in a design and manufacturing advantage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.