Parallel signal bus with reduced miller effect capacitance
US5649126A · kind A · utility
5Cited by
8References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1995 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Dec 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4077
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel signal bus for conveying a plurality of logic signals with reduced Miller effect capacitance includes adjacent, parallel signal lines with inverting buffer amplifiers whose respective positions are staggered both longitudinally along the signal lines and latitudinally with respect to their adjacent signal lines. With such a staggered configuration, the resulting Miller effect capacitance which would otherwise result from adjacent signal lines being driven at opposing polarities is reduced, on average, by approximately half.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.